The future of chip manufacturing involves creating denser and more complicated chip designs. The trend to maximize the performance of a chip has been to construct chips that incorporate more processing cores per chip. The designers of future product families envision many cores per chip, each with their own cache hierarchy.
Customers with a capacity-on-demand (COD) feature pay only for the chip cores that they use even though the system or chip may have more cores. These cores are enabled on demand. Until the time the customer pays for additional cores these cores are left disabled or in some “sleep” state. Some high end systems will have spare cores by design. This is in addition to cores left for COD. Thus, there are three types of cores, enabled, spare and disabled cores. The spare cores will not be enabled at all as customers will never be allowed to use these cores. These spare cores will be used for multiple purposes, such as, for example, (1) to replace failed cores, 2) for partition allocation where spares will be used to contain partitions but will not reduce the number of spares in the system, and 3) for load balancing in micro-partitioned systems, where spares will be used in lieu of remote cores for dispatching without increasing the enabled cores in the system. Therefore some cores in the system will always be disabled either for spares or for other purposes.
Thus, there is a need to provide an improved methodology to improve the overall system performance by taking advantage of available but unused cache capacity.